1. Field of the Invention
The present invention relates to a layout designing method and a layout designing apparatus, and more particularly to a method and apparatus for designing the hierarchical layout of an LSI.
2. Description of the Related Art
Of late, in accordance with an improvement in the density/performance of an LSI, a hierarchical designing technique has become used also to design layout. In particular, a top-down designing technique by which the design of a whole chip can be evaluated at an early stage has become important. In this designing technique, a floorplan for a chip, that is, the arrangement of hard and soft macros and the formation of schematic wiring paths for wires to connect those macros are firstly performed.
FIG. 8 is a flowchart showing a conventional method for designing the hierarchical layout of an LSI . FIGS. 9A, 9B, 10A and 10B illustrate examples of the layout designed by the hierarchical layout designing method shown in FIG. 8.
The conventional hierarchical layout designing method will now be described with reference to FIGS. 8 to 10B.
First of all, the area of a soft macro is evaluated using a calculation formula (step S70). As a method for evaluating the area, the technique disclosed by, for example, Published Unexamined Japanese Patent Application (Kokai) No. 08077225, can be employed. The contents of Japanese Patent Application No. 08077225 are incorporated in the present specification for reference.
Next, hard and soft macros are placed (step S71).
Following the above, the shape of the placed soft macro is modified so that a useless empty area does not occur on the chip (step S72).
FIG. 9A shows a plane of the LSI after the steps S70 to S72 have been executed. Hard macros 86 to 88 and a soft macro 89 are placed in a chip frame 85.
Thereafter, schematic wiring is performed on chip level such that schematic wiring paths are formed (step S73). In order to attain the performance required of this LSI, the wiring paths need to be as short as possible. In consideration of this, wires may be formed along paths which pass above the soft macro, if necessary. For example, when the hard macro 91 and the soft macro 93 need to be connected to each other as shown in FIG. 9B, wiring paths 95 which pass the soft macro 94 are preferred.
At that stage, the amount of signal delay is checked on chip level (step S74), and a determination is performed as to whether design constraints have been fulfilled or not (step S75). If the design constraints have not been fulfilled, the steps after the step S71, such as the rearrangement of the soft macro and so on, are repeated. If the design constraints have been fulfilled, the soft macro is extracted (step S76), and the internal layout of the soft macro is initiated (steps S77 to S83).
As regards the internal layout of the soft macro, all wires need to be completed with the wiring paths, which have been determined in the floorplan and which pass the soft macro, being kept as they are to the utmost.
A process for designing the internal layout of the soft macro will now be explained.
Firstly, cell rows in which cells are to be placed are formed (step S77). The direction in which the cell rows are formed is randomly determined by a designer. The number of cell rows is evaluated using a predetermined calculation formula. The size (the lateral width and height) of the soft macro varies when the number of cell rows is changed.
A wiring which can pass above the cell rows has constraints on its wiring layer, the wiring direction and the number of wires forming the wiring. The direction of the cell rows greatly influences whether the internal wiring of the soft macro and the wires forming the wiring which passes the soft macro can be formed along predetermined paths. FIGS. 10A and 10B show this matter.
In FIG. 10A, cell rows 98 extend in the soft macro 96 in a direction along the x-axis (an x-axial direction). A wiring (passing wiring) 97 is formed a certain layer and is predetermined to pass above the soft macro 96, during the layout design performed on chip level.
When the cells are placed in the cell rows, many of the wires forming the passing wiring 97 cannot be formed along the designed paths in the case where the cells have areas (obstructed areas) 99 which the passing wiring 97 I not allowed to pass, for example, areas where the passing wiring 97, if formed passing those areas, would meet the internal wiring of the cells. Under this condition, the wires have to be formed along paths slightly different from those designed, and the amount of space occupied by the wires is large.
In FIG. 10B, cell rows 102 extend in a soft macro 100 in a direction along the y-axis (an y-axial direction). In this case, the obstructed areas 103 of the cell rows 102 do not obstruct the passage of a passing wiring 101.
Actually the relationship between a wiring layer and an area which the wiring layer is not allowed to pass is complicated, and it is difficult for the designer to determine the optimum direction of the cell rows In consideration of this, the cell rows which all soft macros on the chip have are normally designed so as to extend in the same direction. The direction is changed only in the case where the soft macros include a soft macro which is extremely long a vertical direction and/or a soft macro which is extremely long in a lateral direction. The aspect ratio which improves the integration density is known to some extent, the direction according to the aspect ratio is adopted.
Thus, the optimum direction of the cell rows has been conventionally determined based on the experiences of the designer. The wiring efficiency owing to a wiring layer for the passing wiring, the wiring direction and the number of wires is not adequately taken into consideration.
After the cell rows are formed by the step S77, the cells are automatically placed in the cell rows (step S78). Following this, the internal wiring of the soft macro are formed by an automatic schematic wiring procedure (step S79) and an automatic detailed wiring procedure (step S80). As regards those of the wires whose paths have been predetermined and which are to pass the soft macro, changes if being made in their paths will influence the design of the whole chip. Therefore, such wires are formed prior to other wires so that they can be formed along the schematic paths determined in advance.
At this point, it is determined whether all wires have been formed without departing from wiring rules (step S81).
When it is determined that all wires have been formed without departing from the wiring rules, the designing of the internal layout of the soft macro is stopped, the detailed wiring procedure is conducted on chip level (step S82), and the amount of delay is checked again on chip level (steps S83 and S84).
In the case where the wires making up a passing wiring are formed along paths which differ considerably from those designed, it may be determined in the step S84 that the signal delay does not satisfy a predetermined condition.
In that case, the steps after the steps S72 or S77 are repeated, and the interior of the soft macro and the entirety of the chip are redesigned.
Also in the case where the formation of all wires in the soft macro block cannot be completed, the steps after the step S72 or S77 are repeated, and the interior of the soft macro block and the entirety of the chip are redesigned.
Thus, according to the conventional hierarchical layout designing method, there is no means for associating, with each other, the wiring layer of the wiring passing the soft macro, the wiring direction, the number of wires and the direction of the cell rows formed in the soft macro. This entails the possibility of the cell rows being designed so as to extend in such a direction as cannot reserve the paths for the wires. If the cell rows are designed so, the passing wiring will have to be formed avoiding the soft macro, resulting in the wiring being longer than designed. The performance of the chip may not reach the desired level, and wiring procedures may not able to be completed due to the deviation of the wiring in the soft macro from that evaluated. This incurs a problem such as that the designing period become longer than expected due to redesigning.